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Triple-Output Power-Management IC for
Microprocessor-Based Systems
Pin Description (continued)
PIN
20
21
22
23
24
25
28
29
30
32
33
34
36
NAME
OUT1
COMP2
OUTOK
PG2
LX2
INP2
FB2
OUT3
COMP3
PG3
LX3
INP3
LBO
FUNCTION
REG1 Output-Voltage Sense Input. Bypass OUT1 to PG1 with a 10μF or greater low-ESR capacitor
(see the Output Capacitor Selection section).
REG2 Compensation Node. Connect a series resistor and capacitor from COMP2 to GND in parallel
with a 33pF capacitor to compensate REG2 (see the Compensation and Stability section).
Output-OK Output. OUTOK sinks current to GND when the voltage at REG2 is below the regulation
threshold. When the output is in regulation, OUTOK is high impedance. OUTOK is used by the
processor to indicate when it is safe for the processor to exit sleep mode. OUTOK is an open-drain
output. OUTOK maintains a valid low output for IN as low as 1V.
REG2 Power Ground. Connect PG2 directly to a power ground plane. Connect PG1, PG2, PG3, and
GND together at a single point as close to the IC as possible.
REG2 Power-Switching Node. Connect the external inductor of the REG2 output LC filter from LX2 to
OUT2. LX2 discharges OUT2 when REG2 is disabled (see the Inductor Selection section).
REG2 Power Input. Bypass INP2 to PG2 with a 1.0μF or greater low-ESR capacitor. INP1, INP2, INP3,
and IN must be connected together externally. A single 4.7μF capacitor can be used for INP1, INP2,
and INP3.
REG2 Feedback-Sense Input. Set the REG2 output voltage with a resistive voltage-divider from the
REG2 output voltage to FB2. The FB2 regulation threshold is 0.7V. Connect FB2 directly to OUT2 for
an output voltage of 0.7V.
REG3 Output-Voltage Sense Input. Bypass OUT3 to GND with a 10μF or greater low-ESR capacitor
(see the Output Capacitor Selection section).
REG3 Compensation Node. Connect a series resistor and capacitor from COMP3 to GND in parallel
with a 33pF capacitor to compensate REG3 (see the Compensation and Stability section).
REG3 Power Ground. Connect PG3 directly to a power ground plane. Connect PG1, PG2, PG3, and
GND together at a single point as close to the IC as possible.
REG3 Power-Switching Node. Connect the external inductor of the REG3 output LC filter from LX3 to
OUT3 (see the Inductor Selection section).
REG3 Power Input. Bypass INP3 to PG3 with a 1.0μF or greater low-ESR capacitor. INP1, INP2, INP3,
and IN must be connected together externally. A single 4.7μF capacitor can be used for INP1, INP2,
and INP3.
Low-Battery Output. LBO sinks current to GND when the voltage at LBI is below the LBI threshold
voltage; LBO is high impedance when LBI is above the threshold. LBO is an open-drain output. LBO
maintains a valid low output level for IN as low as 1V.
12
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